Arthur T Knackerbracket has processed the following story:
TSMC Readies Lower-Cost 4nm Manufacturing Tech: Up To 8.5% Cheaper
TSMC has unveiled its new 4 nm-class production technology, N4C, a new fabrication process set to enhance the company's 5nm-class production nodes by offering significant cost reductions and optimizing design efficiency.
"We are not done with our 5nm and 4nm [technologies]," said Kevin Zhang, Vice President of Business Development at TSMC, at the company's North American Technology Symposium 2024, where the new process was revealed. "From N5 to N4, we have achieved 4% density improvement optical shrink, and we continue to enhance the transistor performance. Now we bring in N4C to our 4 nm technology portfolio. N4C allows our customers to reduce their costs by remove some of the masks and to also improve on the original IP design like a standard cell and SRAM to further reduce the overall product level cost of ownership."
[...] The introduction of N4C is strategically important for TSMC as it provides a way for customers to significantly lower their production costs for a 4nm-class node, which may drive the adoption of this process technology among customers looking for relatively low costs. The new node promises a well-adjusted combination of power, performance, and area (PPA), making it an attractive option for many of TSMC's clients.
Given the high costs associated with 3nm-class technologies and their relatively limited advantages over nodes like N4P in terms of performance and transistor density, N4C is positioned to be a popular choice.
TSMC expects to start producing chips using the N4C technology in 2025. With six years of experience in 5 nm-class fabrication processes by then, the company anticipates that N4C will achieve good yields and maintain lower costs, reinforcing its appeal as a cost-effective manufacturing solution in the semiconductor industry. In fact, by 2025, many of the fab tools at 5nm-capable fabs will be depreciated, so N4C and similar nodes may actually be cost-effective.
Arthur T Knackerbracket has processed the following story:
TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its current-generation 5nm-class offerings. To that end, at its North American Technology Symposium 2024, the company introduced a new, optimized 5nm-class node: N4C.
[...] "This is a very significant enhancement, we are working with our customer, basically to extract more value from their 4 nm investment," Zhang said.
TSMC expects to start volume production of N4C chips some time next year. And with TSMC having produced 5nm-class for nearly half a decade at that point, N4C should be able to hit the ground running in terms of volume and yields.
(Score: 2, Troll) by Kell on Monday April 29, @02:01AM (1 child)
This story was posted on Saturday and it is now Monday (local time, mate), and this is first post.
Is this story just not interesting to anyone, or is Soylent News now so sparsely populated that there's nobody who cares enough to post?
Scientists ask questions. Engineers solve problems.
(Score: 1, Offtopic) by bzipitidoo on Monday April 29, @03:53AM
Perhaps the story format is not the best format for this kind of info? What's really needed is a Doomsday Clock like continuous monitoring of node size. I was not aware that 4nm production was imminent. 4 minutes before midnight, when the Technological Singularity will arrive!